Systems and methods for dynamically adjusting memory state transition timers

ABSTRACT

Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

DESCRIPTION OF THE RELATED ART

Portable computing devices (e.g., cellular telephones, smart phones, tablet computers, portable digital assistants (PDAs), portable game consoles, wearable devices, and other battery-powered devices) and other computing devices continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful and more complex. Portable computing devices now commonly include a system on chip (SoC) comprising one or more chip components embedded on a single substrate (e.g., one or more central processing units (CPUs), a graphics processing unit (GPU), digital signal processors, etc.). The SoC may be coupled to one or more volatile memory modules or devices, such as, dynamic random access memory (DRAM) via double data rate (DDR) high-performance data and control interface(s).

Existing and future generations of DDR memory (e.g., DDR1, DDR2, DDR3, DDR4, etc.) support two or more memory power states for enabling devices to operate according to desirable power and/or performance modes. At least one of the memory power states may comprise a relatively lower power mode for enabling the device to conserve power. To control the transition between memory power states, DDR memory devices have clock timer settings (e.g., a power down timer, a page close timer, a self-refresh timer), which may impact the idle time duration required to enter the lower power mode. In existing designs, for example, SoC and system manufacturers may program static values for the idle timers based on lab simulation and test results. The static idle timer values may be determined to provide power and performance for overall key use cases. In operation, the predetermined static idle timer values are used regardless of the various use case changes, DDR types and models, changes in power versus performance priority, etc.

When entering the lower power memory state, however, the use of predetermined static settings for the idle timers may yield less than an optimal power and/or performance due to dynamically changing factors. For example, the optimal idle timer values may vary depending on DDR types, models, and generations, as well as changing operational factors, such as, memory traffic patterns, memory operating frequencies, memory traffic amounts, and power versus performance priorities.

Accordingly, there is a need for improved systems and methods for dynamically adjusting memory power state transition timers.

SUMMARY OF THE DISCLOSURE

Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

Another embodiment is a computer system. The computer system comprises a memory device and a system on chip (SoC). The SoC comprises a processor and a memory controller. The memory controller is electrically coupled to the memory device. The processor executes a memory scheduler configured to determine an optimal value for one or more memory power state transition timer settings used by the memory controller to enter a low power memory state.

BRIEF DESCRIPTION OF THE DRAWINGS

In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102A” or “102B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.

FIG. 1 is a block diagram of an embodiment of a system for dynamically adjusting memory power state transition timers.

FIG. 2 is a flowchart illustrating an embodiment of a method implemented in the system of FIG. 1 for dynamically adjusting memory power state transition timers.

FIG. 3 is a block diagram illustrating the data inputs and outputs of an embodiment of the memory power state transition manager of FIG. 1.

FIG. 4 is a timing diagram illustrating exemplary embodiments of idle timers that may be dynamically adjusted to optimize power consumption in a lower power state of dynamic random access memory (DRAM) device.

FIG. 5 is a block diagram illustrating an embodiment of a look-up table for determining optimal power down timer and page down timer settings based on a memory utilization percentage and a memory operating frequency.

FIG. 6 is a graph illustrating an embodiment of an iterative search method for determining optimal idle timer settings.

FIG. 7 is a block diagram illustrating another embodiment of a look-up table for determining optimal power down timer and page down timer settings based on use case types.

FIG. 8 is a block diagram of an embodiment of a portable communication device for incorporating the system of FIG. 1.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

In this description, the term “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

As used in this description, the terms “component,” “database,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

In this description, the terms “communication device,” “wireless device,” “wireless telephone”, “wireless communication device,” and “wireless handset” are used interchangeably. With the advent of third generation (“3G”) wireless technology and four generation (“4G”), greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities. Therefore, a portable computing device may include a cellular telephone, a pager, a PDA, a smartphone, a navigation device, or a hand-held computer with a wireless connection or link.

FIG. 1 illustrates a system 100 comprising a system on chip (SoC) 102 electrically coupled to one or more memory devices 104. The SoC 102 comprises various on-chip components interconnected via a SoC bus 114. In the embodiment of FIG. 1, the SoC 102 comprises one or more memory clients that request memory resources from the memory device(s) 104. The memory clients may comprise one or more processing units (e.g., central processing unit (CPU) 106, a graphics processing unit (GPU), a digital signal processor (DSP), etc.), a video encoder, or other clients requesting read/write access to the memory device(s) 104. The SoC 102 may further comprise on-chip memory, such as, static random access memory (SRAM) 110 and read only memory (ROM) 112.

It should be appreciated that the system 100 may be implemented in any computing device, including a personal computer, a workstation, a server, a portable computing device (PCD), such as a cellular telephone, a smartphone, a portable digital assistant (PDA), a portable game console, a navigation device, a tablet computer, a wearable device, such as a sports watch, a fitness tracking device, etc., or other battery-powered, web-enabled devices.

Memory controller 108 on SoC 102 is electrically coupled to the memory device(s) 104 via a bus 124. Memory controller 108 manages the flow of data going to and from the memory device(s) 104. Memory controller 108 generally comprises the logic for reading and writing to the memory device(s) 104. In an embodiment, the memory device(s) 104 comprise dynamic random access memory (DRAM) device(s) and the bus 124 comprises a high-performance random access memory (RAM) bus. The memory controller 108 and the DRAM devices may support any existing or future generations of double data rate (DRR) interfaces (e.g., DDR1, DDR2, DDR3, DDR4, etc.).

The memory device(s) 104 and the memory controller 108 may be configured to support two or more memory power states or modes. Each memory power state or mode may be selectively controlled by the memory controller 108 to provide different combinations of memory power consumption and/or memory performance. At least one of the memory power states comprises a relatively lower power memory state for conserving memory power consumption. As further illustrated in FIG. 1, an operating system (O/S 116) executed by the CPU 106 may comprise a memory manager 118. The memory manager 118 generally comprises the logic for allocating memory in the memory device(s) 104 to memory clients. The memory manager 118 may comprise a scheduler component 120 for scheduling memory read/write operations to the memory device(s) 104. The memory manager 118 may further comprise a memory power state transition timer optimization component 122, which generally comprises the logic for dynamically adjusting one or more timer settings used by the memory device(s) 104 to transition from one memory power state to another power state. In an embodiment, the memory power state transition timer optimization component 122 is configured to determine optimal power-saving values for the one or more timer settings used to enter a lower power memory state. The memory power state transition timer optimization component 122 may be implemented in the O/S/116, as illustrated in FIG. 1, or in hardware or firmware.

FIG. 2 illustrates an embodiment of a method 200 implemented in the system 100 for dynamically adjusting memory power state transition timers to yield a power savings in a low power memory state. At block 202, the memory power state transition timer optimization component 122 may receive one or more parameters impacting the usage or performance of the memory device 104. It should be appreciated that the received parameters may be monitored via the operating system 116, the memory manager 118, and/or the scheduler 120. Furthermore, the received parameters may vary depending on, for example, the type of memory device or other components in the system 100. In an embodiment, the received parameters may comprise information related to one or more of the following: memory traffic pattern(s), memory operating frequencies, memory traffic amounts, memory utilization percentage, power and/or performance priorities, system use cases, and types of applications executing. The received parameters may also identify a type, model, and or vendor for the memory device(s) 104.

At block 204, the memory power state transition timer optimization component 122 may determine, based on the one or more received parameters, whether current values for one or more memory power state transition timer settings are to be updated. The memory power state transition timer optimization component 122 may monitor and detect dynamic changes in the received parameters to determine whether current values for the memory power state transition timers are less than optimal for power conservation in the low power memory state. It should be appreciated that the memory power state transition timers may vary depending on the type, generation, model, etc. of the memory device(s) 104. For example, in embodiments where the memory device(s) 104 comprise DRAM, the timers may comprise DDR idle timers such as, for example, a power down timer, a page close timer, or a self-refresh timer.

Regardless the type of memory power state transition timer(s), if the current values are no longer optimally power-saving, new values may be determined based on the received parameters. The new values may be calculated or determined via, for example, a look-up table or other optimization logic. At block 206, the memory power state transition timer optimization component 122 may update the values for the memory power state transition timers with an optimal value based on or more of the received parameters. The optimal value may be provided to and stored in the memory controller 108 for use when entering the low power memory state (block 208).

FIG. 3 is a block diagram illustrating exemplary data inputs and outputs for an embodiment of the memory power state transition timer optimization component 122. In this embodiment, the memory power state transition timer optimization component 122 is configured to determine optimal values for DDR idle timer settings 312 used by DRAM devices to enter a low power memory state. A DRAM controller 304 may store current values for the DDR idle timer settings 312 in one or more registers 310. During system operation, the memory power state transition timer optimization component 122 may monitor and/or receive various data inputs 302, as illustrated at arrow 306. The data inputs 302 may comprise various information related to memory usage such as, for example, memory traffic patterns, memory operating frequencies, memory traffic amounts or utilization percentage, and the memory device type, vendor, or model. The data inputs 302 may also comprise information related to memory power and/or performance priorities or modes, application(s) being executed, battery life remaining, or any other conditions or parameters that may impact the optimal values for the DDR idle timer settings.

FIG. 4 is a timing diagram 400 illustrating the operation of various exemplary DDR idle timers that may be dynamically adjusted by the memory power state transition timer optimization component 122. Timing diagram 400 shows operation of a power down idle timer 402, a page close idle timer 404, and a self-refresh idle timer 406. The duration of idle timers 402, 404, and 406 may be controlled by corresponding idle timer settings 312 stored in the register(s) 310. In the example of FIG. 4, the power down idle timer 402 has a current value of 64 DDR clock cycles. The page close idle timer 404 has a current value of 128 DDR clock cycles. The self-refresh idle timer 404 has a current value of 50 cycles of a crystal oscillator. Referring again to FIG. 3, the memory power state transition timer optimization component 122 may determine optimal values for timers 402, 404, and 406 based on the data inputs 302.

It should be appreciated that the optimal values may be determined in various ways. In one embodiment, the memory power state transition timer optimization component 122 accesses a look-up table to determine the idle timer settings (i.e., data output(s)) that correspond to one or more of the data inputs 302. FIG. 5 illustrates a look-up table 500 for determining optimal power down timer and page down timer settings based on a memory utilization percentage and a memory operating frequency. Column 502 illustrates values for combinations of a memory utilization percentage 506 and a DDR frequency 508. For each combination of input values in column 502, the table 500 lists the corresponding output values in column 504. The corresponding output value for the power down timer is identified in column 510, and the corresponding output value for the page close timer is identified in column 512. For example, referring to the top row in table 500, if the memory utilization percentage is less than 30% and the DDR frequency is 200 MHz, the look-up table 500 determines that the values for the power down timer and the page close timer should be updated to 4 and 64 DDR cycles, respectively. It should be appreciated that the inputs 502 and outputs 504 may be based on simulated data and programmed into the registers 310 as default values.

FIG. 7 illustrates another embodiment of a look-up table 700 for determining the optimal power down timer and page close timer settings based on use case types. The use case types listed in column 706 define the table inputs. For each use case type, the table 700 lists the corresponding output values in column 704. The corresponding output value for the power down timer is identified in column 708, and the corresponding output value for the page close timer is identified in column 710. In the example of FIG. 7, the use case types may comprise one or more of the following: a voice call using wideband code division multiple access (WCDMA) or Global System for Mobile Communication (GSM); a voice call over Long-Term Evolution (LTE); LTE data downloading; graphics benchmark application; DDR benchmark application; or any other use cases. It should be appreciated that the inputs 702 and outputs 704 may also be based on simulated data and programmed into the registers 310 as default values. In other embodiments, the memory power state transition timer optimization component 122 may be configured to calculate the optimal values for the DDR idle timer settings based on an average idle timer duration.

FIG. 6 is a graph 600 illustrating another embodiment for determining the optimal idle timer settings using an iterative search method. The x-axis represents values for the page close timer, and the y-axis represents values for the power down timer. During operation of the system 100, a search algorithm may iteratively search for optimal x and y values that yield a lower average memory power. In the example of FIG. 6, the search method may start with an initial value combination at X0. The search algorithm may estimate power and/or performance for adjacent value combinations. As illustrated in FIG. 6, adjacent values with larger and smaller values for both the power down timer and the page close timer may be searched to determine whether an adjacent value yields better power and/or performance. The search method may be configured to iteratively identify subsequent value combinations X1, X2, X3, etc. until an optimal value combination is determined that yields the lowest possible average memory power.

As mentioned above, the system 100 may be incorporated into any desirable computing system. FIG. 8 illustrates the system 100 incorporated in an exemplary portable computing device (PCD) 800. It will be readily appreciated that certain components of the system 100 are included on the SoC 322 while other components (e.g., the DRAM 104) are external components coupled to the SoC 322. The SoC 322 may include a multicore CPU 802. The multicore CPU 802 may include a zeroth core 810, a first core 812, and an Nth core 814. One of the cores may comprise, for example, a graphics processing unit (GPU) with one or more of the others comprising the CPU.

A display controller 328 and a touch screen controller 330 may be coupled to the CPU 802. In turn, the touch screen display 806 external to the on-chip system 322 may be coupled to the display controller 328 and the touch screen controller 330.

FIG. 8 further shows that a video encoder 334, e.g., a phase alternating line (PAL) encoder, a sequential color a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the multicore CPU 802. Further, a video amplifier 336 is coupled to the video encoder 334 and the touch screen display 806. Also, a video port 338 is coupled to the video amplifier 336. As shown in FIG. 8, a universal serial bus (USB) controller 340 is coupled to the multicore CPU 802. Also, a USB port 342 is coupled to the USB controller 340. Memory 104 may be coupled to the SoC 322 (as illustrated in FIG. 1).

Further, as shown in FIG. 8, a digital camera 348 may be coupled to the multicore CPU 802. In an exemplary aspect, the digital camera 348 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

As further illustrated in FIG. 8, a stereo audio coder-decoder (CODEC) 350 may be coupled to the multicore CPU 802. Moreover, an audio amplifier 352 may coupled to the stereo audio CODEC 350. In an exemplary aspect, a first stereo speaker 354 and a second stereo speaker 356 are coupled to the audio amplifier 352. FIG. 8 shows that a microphone amplifier 358 may be also coupled to the stereo audio CODEC 350. Additionally, a microphone 360 may be coupled to the microphone amplifier 358. In a particular aspect, a frequency modulation (FM) radio tuner 362 may be coupled to the stereo audio CODEC 350. Also, an FM antenna 364 is coupled to the FM radio tuner 362. Further, stereo headphones 366 may be coupled to the stereo audio CODEC 350.

FIG. 8 further illustrates that a radio frequency (RF) transceiver 368 may be coupled to the multicore CPU 802. An RF switch 370 may be coupled to the RF transceiver 368 and an RF antenna 372. A keypad 204 may be coupled to the multicore CPU 802. Also, a mono headset with a microphone 376 may be coupled to the multicore CPU 802. Further, a vibrator device 378 may be coupled to the multicore CPU 802.

FIG. 8 also shows that a power supply 380 may be coupled to the on-chip system 322. In a particular aspect, the power supply 380 is a direct current (DC) power supply that provides power to the various components of the PCD 800 that require power. Further, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.

FIG. 8 further indicates that the PCD 800 may also include a network card 388 that may be used to access a data network, e.g., a local area network, a personal area network, or any other network. The network card 388 may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PeANUT) network card, a television/cable/satellite tuner, or any other network card well known in the art. Further, the network card 388 may be incorporated into a chip, i.e., the network card 388 may be a full solution in a chip, and may not be a separate network card 388.

As depicted in FIG. 8, the touch screen display 806, the video port 338, the USB port 342, the camera 348, the first stereo speaker 354, the second stereo speaker 356, the microphone 360, the FM antenna 364, the stereo headphones 366, the RF switch 370, the RF antenna 372, the keypad 374, the mono headset 376, the vibrator 378, and the power supply 380 may be external to the on-chip system 322.

It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions, such as the modules described above. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.

Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.

Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.

Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.

In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.

Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims. 

What is claimed is:
 1. A method for dynamically adjusting memory power state transition timers, the method comprising: receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device; based on the one or more parameters, determining an optimal value for one or more memory power state transition timer settings; and updating a current value for the memory power state transition timer settings with the optimal value.
 2. The method of claim 1, wherein the one or more parameters impacting usage or performance of the memory device comprises one or more of a memory traffic pattern, a memory operating frequency, a memory traffic amount, a memory utilization percentage, and a power/performance mode.
 3. The method of claim 1, wherein the memory power state transition timer settings comprise an idle timer setting for entering a lower power memory state.
 4. The method of claim 1, wherein the receiving one or more parameters impacting usage or performance of the memory device comprises: monitoring and detecting a change in the one or more parameters.
 5. The method of claim 1, wherein the determining the optimal value for the one or more memory power state transition timer settings comprises: accessing a look-up table to determine the optimal value based on the one or more parameters.
 6. The method of claim 1, wherein the determining the optimal value for the one or more memory power state transition timer settings comprises calculating the optimal value based on an average idle timer duration.
 7. The method of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device, and the memory power state transition timer settings comprise a power down timer setting and a page down timer setting for transitioning the DRAM device to a low power mode.
 8. The method of claim 1, wherein the determining the optimal value for the one or more memory power state transition timer settings comprises an iterative search of a plurality of setting values.
 9. A system for dynamically adjusting memory power state transition timers, the system comprising: means for receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device; means for determining an optimal value for one or more memory power state transition timer settings based on the one or more parameters; and means for updating a current value for the memory power state transition timer settings with the optimal value.
 10. The system of claim 9, wherein the one or more parameters impacting usage or performance of the memory device comprises one or more of a memory traffic pattern, a memory operating frequency, a memory traffic amount, a memory utilization percentage, and a power/performance mode.
 11. The system of claim 9, wherein the memory power state transition timer settings comprise an idle timer setting for entering a lower power memory state.
 12. The system of claim 9, wherein the means for receiving one or more parameters impacting usage or performance of the memory device comprises: means for monitoring and detecting a change in the one or more parameters.
 13. The system of claim 9, wherein the means for determining the optimal value for the one or more memory power state transition timer settings comprises: means for accessing a look-up table to determine the optimal value based on the one or more parameters.
 14. The system of claim 9, wherein the means for determining the optimal value for the one or more memory power state transition timer settings comprises means for calculating the optimal value based on an average idle timer duration.
 15. The system of claim 9, wherein the memory device comprises a dynamic random access memory (DRAM) device, and the memory power state transition timer settings comprise a power down time setting and a page down timer setting for transitioning the DRAM device to a low power mode.
 16. The system of claim 9, wherein the means for determining the optimal value for the one or more memory power state transition timer settings comprises a means for iteratively searching of a plurality of setting values.
 17. A computer program embodied in a computer readable medium and executable by a processor for dynamically adjusting memory power state transition timers, the computer program comprising logic configured to: receive one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device; based on the one or more parameters, determine an optimal value for one or more memory power state transition timer settings; and update a current value for the memory power state transition timer settings with the optimal value.
 18. The computer program of claim 17, wherein the one or more parameters impacting usage or performance of the memory device comprises one or more of a memory traffic pattern, a memory operating frequency, a memory traffic amount, a memory utilization percentage, and a power/performance mode.
 19. The computer program of claim 17, wherein the memory power state transition timer settings comprise an idle timer setting for entering a lower power memory state.
 20. The computer program of claim 17, wherein the logic configured to determine the optimal value for the one or more memory power state transition timer settings comprises logic configured to: access a look-up table to determine the optimal value based on the one or more parameters.
 21. The computer program of claim 17, wherein the logic configured to determine the optimal value for the one or more memory power state transition timer settings comprises logic configured to: calculate the optimal value based on an average idle timer duration.
 22. The computer program of claim 17, wherein the memory device comprises a dynamic random access memory (DRAM) device, and the memory power state transition timer settings comprise a power down time setting and a page down timer setting for transitioning the DRAM device to a low power mode.
 23. The computer program of claim 17, wherein the logic configured to determine the optimal value for the one or more memory power state transition timer settings comprises an iterative search of a plurality of setting values.
 24. A computer system comprising: a memory device; a system on chip (SoC) comprising a processor and a memory controller, the memory controller electrically coupled to the memory device; and a memory scheduler executed by the processor, the memory scheduler configured to determine an optimal value for one or more memory power state transition timer settings used by the memory controller to enter a low power memory state.
 25. The computer system of claim 24, wherein the optimal value for the one or more memory power state transition timer settings is determined by monitoring one or more parameters impacting usage or performance of the memory device.
 26. The computer system of claim 25, wherein the one or more parameters impacting usage or performance of the memory device comprises one or more of a memory traffic pattern, a memory operating frequency, a memory traffic amount, a memory utilization percentage, and a power/performance mode.
 27. The computer system of claim 25, wherein the memory power state transition timer settings comprise an idle timer setting.
 28. The computer system of claim 25, wherein the optimal value for the one or more memory power state transition timer settings is determined by accessing a look-up table.
 29. The computer system of claim 25, wherein the optimal value is calculated based on an average idle timer duration.
 30. The computer system of claim 25, wherein the memory device comprises a dynamic random access memory (DRAM) device, and the memory power state transition timer settings comprise a power down time setting and a page down timer setting for entering the low power memory state. 